LLM-assisted Path Exploration for RTL Verification

Coverage-driven simulation is a widely adopted method for verifying hardware designs. Nevertheless, achieving satisfactory coverage remains a challenge, even with millions of tests applied to modern industrial designs. To tackle this issue, Concolic testing, which combines concrete simulation with symbolic execution, has been introduced to guide simulations through targeted branch mutations. However, traditional path exploration heuristics in Concolic testing are typically manually crafted for specific scenarios, which limits their broader applicability. In this paper, we propose an innovative approach that harnesses large language models (LLMs) to analyze the structure and semantics of Register Transfer Level (RTL) designs. By integrating LLMs into the Concolic testing framework, our method improves path selection by utilizing both static structural features and dynamic simulation data. Recognizing that LLMs are primarily trained for general-purpose tasks, we enhance their effectiveness in hardware verification by constructing a synthetic training corpus and fine-tuning the models accordingly. Our experimental results demonstrate that this approach significantly enhances branch coverage during Concolic testing while incurring negligible overhead.