Machine-Learning Driven Cell Library Compaction

As the number of standard cells continues to grow to accommodate the various layout characteristics (e.g., area, delay, power, pin accessibility), the task of generating a cell library of reasonable size that is the best suited for EDA tools to optimize the PPA (power, performance, area) of chip implementation is utmost important. This work proposes an ML (machine-learning) driven solution to the cell library compaction problem. Precisely, we build two ML models: (1) modulating input cell features considering input design features, by which we linearly transform the cell features according to the input design context. We build up our ML model on the FiLM (feature-wise linear modulation) platform; (2) element-wise similarity derivation, which is used to identify a collection of cells that are highly related to each other in optimizing the PPA of design implementation. We employ the MHSA (multi-head self-attention) mechanism to build our ML model. Through experiments with benchmark circuits, it is shown that the chip implementations produced by our ML-driven method of cell library compaction is able to use on average 2.3% smaller chip area, 4.6% less power, similar clock frequency, and 37.9% shorter EDA tool runtime than that produced by the prior best state-of-the-art method of cell library compaction.