Machine Learning Driven Early Clustering for Multi-bit Flip-Flop Allocation
This paper presents a new approach to the problem of allocating multi-bit flip-flops (MBFFs) for low power. The prior approaches have solved the MBFF allocation problem sequentially by addressing two sub-problems: (1) placing individual flip-flops considering the circuit timing and wirelength constraints, and (2) clustering the flip-flops to form MBFFs in a way to minimize the area of standard cells and clock network power consumption under the physical proximity constraints. Yet, there is no easy way to reliably predict the solution quality of sub-problem 2 during the process of solving sub-problem 1. In our approach, we place the primary importance on minimizing power consumption. Consequently, we try to minimize power consumption by clustering flip-flops first, utilizing a graph neural network (GNN) based prediction model, and then placing the resulting MBFFs later. This is the first method to cluster multi-bit flip-flops without using the positions of single-bit flip-flops, by modifying the netlist at an early stage of the physical design. Through experiments with benchmark circuits, it is shown that our approach of early consideration of clustering flip-flops is very effective, significantly reducing the power consumption by about 21% while satisfying all the timing constraints over that of the conventional approach with single-bit flip-flops.
Authors
- Jooyeon Jeong (ORCID: https://orcid.org/0000-0003-2789-9485)
- Taewhan Kim (ORCID: https://orcid.org/0000-0003-2376-4970)
Institutions
- Seoul National University (KR)
Publication Details
- Published
- 2025-09-08
- DOI
- https://doi.org/10.1109/mlcad65511.2025.11189132
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00