Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Ferroelectric random-access memory (FeRAM) is a promising candidate for energy-efficient non-volatile memory, particularly for logic-in-memory and compute-in-memory applications. Among the available cell architectures, 1T–nC and 2T–nC FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling (XY/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using TCAD and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node dynamics, which together dictate sense margin and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the sense margin from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T–nC suffers more from charge sharing with the bitline, while 2T–nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T–nC and 2T–nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.