Ultrasteep Subthreshold Slope Metal-Drain Dual-Type (p/n) Silicon Transistors: Characterization, Analysis, and Application

The switching efficiency of conventional silicon-based field-effect transistors (FETs) is fundamentally constrained by their 60-mV/dec subthreshold swing (SS) lower bound. Recently, we proposed an Al-drain FET to overcome this limitation. In this work, we further design and experimentally demonstrate dual types of (p/n) silicon transistors featuring various metal-drain (MD) structure MD field effect transistor (MDFET). Particularly, Al and Ti are selected for n-type MDFET, while Pt is adapted for p-type MDFET based on their work function. Measurement results show that both n-type and p-type MDFETs achieve ultrasteep average SS (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\ll$</tex-math> </inline-formula> 10 mV/dec) over multiple decades of current. In addition, TCAD simulations have been performed, and the simulation results agree well with experimental data qualitatively. Detailed analysis reveals that the Schottky junction at the metal–silicon drain interface induces a localized electric field amplification (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gt 1.66\times $</tex-math> </inline-formula> compared to conventional doped silicon drain) and extends the depletion region, synergistically enhancing impact ionization (II) of carriers. This mechanism establishes a regenerative feedback loop, enabling ultrasteep switching behavior. Finally, a compact model of MDFET is created for circuit simulation, and an inverter circuit composed of pMOS and n-type MDFET is constructed experimentally. Both measured data and model simulation agree well, illustrating the potential of MDFET for CMOS-compatible low-power logic applications.