Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSI

Accurate graph similarity is critical for knowledge transfer in VLSI design, enabling the reuse of prior solutions to reduce engineering effort and turnaround time. We propose Pieceformer, a scalable, self-supervised similarity assessment framework, equipped with a hybrid message-passing and graph transformer encoder. To address transformer scalability, we incorporate a linear transformer backbone and introduce a partitioned training pipeline for efficient memory and parallelism management. Evaluations on synthetic and real-world CircuitNet datasets show that Pieceformer reduces mean absolute error (MAE) by 24.9% over the baseline and is the only method to correctly cluster all real-world design groups. We further demonstrate the practical usage of our model through a case study on a partitioning task, achieving up to 89% runtime reduction. These results validate the framework’s effectiveness for scalable, unbiased design reuse in modern VLSI systems.

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Publication Details

Published
2025-09-08
DOI
https://doi.org/10.1109/mlcad65511.2025.11189177
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
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article

Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSI

Yong Liu, Cong Hao, Yusheng Hu, Hang Yang
VLSI and Analog Circuit Testing
article

Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSI

Yong Liu, Cong Hao, Yusheng Hu, Hang Yang
article en

Abstract

Accurate graph similarity is critical for knowledge transfer in VLSI design, enabling the reuse of prior solutions to reduce engineering effort and turnaround time. We propose Pieceformer, a scalable, self-supervised similarity assessment framework, equipped with a hybrid message-passing and graph transformer encoder. To address transformer scalability, we incorporate a linear transformer backbone and introduce a partitioned training pipeline for efficient memory and parallelism management. Evaluations on synthetic and real-world CircuitNet datasets show that Pieceformer reduces mean absolute error (MAE) by 24.9% over the baseline and is the only method to correctly cluster all real-world design groups. We further demonstrate the practical usage of our model through a case study on a partitioning task, achieving up to 89% runtime reduction. These results validate the framework’s effectiveness for scalable, unbiased design reuse in modern VLSI systems.

Georgia Institute of Technology (US), Cadence Design Systems (United States) (US)
Openalex Percentile: Top 69%
VLSI and Analog Circuit Testing
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