A novel cost-effective layout-aware quantum circuit synthesis of symmetric functions on triangular, square, and heavy-hex layouts

Abstract The quantum layout and the mapping of logical to physical qubits are crucial in quantum circuit synthesis for a real quantum computer. In particular, circuits containing large n -bit Toffoli gates ( $$n>3$$ ), such as those derived from cost-expensive gate constructions and hard-to-decompose Exclusive-or Sum of Products (ESOP) expressions, have complications with effective mappings into contemporary quantum layouts, including square grid and heavy-hex layouts. These complications are primarily caused by the limited connectivity among the physical qubits in such layouts, leading to the addition of many SWAP gates. This paper presents several contributions to address these challenges for cost-effectively constructing circuits for totally, generalized, and conditionally symmetric functions. Firstly, we introduce a novel quantum circuit synthesis methodology for such functions based on Reed–Muller Lattices, leveraging Positive and Negative Davio expansions as intermediate representations. Secondly, we present the SWAT gate, a composite operation consisting of a 2-qubit SWAP gate followed by a 3-qubit Toffoli gate, designed to reduce mapping overhead. Thirdly, we demonstrate the effectiveness of our approach on existing industrial quantum architectures by achieving cost-efficient mappings onto square grid and heavy-hex quantum layouts without introducing additional SWAP gates when using the SWAT gate. Finally, we introduce a speculative triangular layout and corresponding layout-aware circuit constructions, serving as a theoretical framework for evaluating synthesis efficiency under enhanced connectivity assumptions. Overall, our research, benchmarked against ESOP-based and BDD-based synthesis methods, demonstrates that Reed–Muller Lattices provide a powerful approach for the layout-aware quantum circuit synthesis of symmetric and related functions, with significant potential to reduce mapping overhead in near-term quantum architectures.