Design Optimization of CMOS Folded-Cascode OTAs via Multi-Objective Evolutionary Algorithms: PSO, DE, and CSPSO Approaches

Objectives: Automatic analog circuit design techniques are required to handle the increasing complexity of the circuit with technological advances. To provide better scalability, reliability, and higher convergence speed, the development and assessment of hybrid optimization algorithms are essential. Method: A hybrid Cuckoo Search–Particle Swarm Optimisation (CSPSO) algorithm was implemented for automatically finding of W/L ratios of each transistor in a Folded Cascode OTA (FOTA) circuit. The results of this blended algorithm were evaluated with the results of Particle Swarm Optimisation (PSO) and Differential Evolution (DE) algorithms in 0.18 µm and 0.35 µm CMOS processes. All the algorithms were programmed in the C language, merged with an NGSPICE file of the circuit, and executed on an Intel® Core™ i5 machine running Ubuntu. Findings: The hybrid CSPSO obtained all the desired specifications in 9 out of 10 runs in the 0.35 µm CMOS process for the circuit of FOTA, while PSO and DE algorithms required 8 out of 10 and 5 out of 10 runs to achieve the target specifications. The results demonstrate that the hybrid CSPSO performs better than the other two algorithms in terms of robustness and success rate. In the 0.18µm case, CSPSO and DE succeeded in all runs, whereas PSO showed limited reliability. Novelty: This research work implements a blended CSPSO algorithm for automated sizing of the FOTA circuit and obtains a better convergence speed compared to traditional DE and PSO. These findings establish CSPSO as a highly effective and scalable optimization paradigm for automated analog circuit design across technology nodes. Keywords: EA, DE algorithm, PSO algorithm, CSPSO algorithm