Further characterisation of Digital Pixel Test Structures implemented in a 65 nm CMOS process

The next generation of MAPS for future tracking detectors will have to meet stringent requirements placed on them. One such detector is the ALICE ITS3 that aims to be very light at 0.07 % X/X 0 per layer and have a low power consumption in the active area of 40 mW/cm 2 by implementing wafer-scale MAPS bent into cylindrical half layers. To address these challenging requirements, the ALICE ITS3 project, in conjunction with the CERN EP R&D on monolithic pixel sensors, proposed the Tower Partners Semiconductor Co. 65 nm CMOS process as the starting point for the sensor. After the initial results confirmed the detection efficiency and radiation hardness, the choice of the technology was solidified by demonstrating the feasibility of operating MAPS in low-power consumption regimes, < 50 m W / c m 2 , while maintaining high-quality performance. This was shown through a detailed characterisation of the Digital Pixel Test Structure (DPTS) prototype exposed to X-rays and ionising beams, and the results are presented in this article. Additionally, the sensor was further investigated through studies of the fake-hit rate, the linearity of the front-end in the range 1.7–28 keV, the performance after ionising irradiation, and the detection efficiency of inclined tracks in the range 0–45°.

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Journal
Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment
Published
2025-10-15
DOI
https://doi.org/10.1016/j.nima.2025.171082
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
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article

Further characterisation of Digital Pixel Test Structures implemented in a 65 nm CMOS process

L. Lautner, W. Snoeys, Artem Kotliarov, Han-Gi Jang et al.
Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment
Integrated Circuits and Semiconductor Failure Analysis
article

Further characterisation of Digital Pixel Test Structures implemented in a 65 nm CMOS process

L. Lautner, W. Snoeys, Artem Kotliarov, Han-Gi Jang, A. Andronic, G. L. Usaı́, W. Deng, Justus Braach, P. Martinengo, M. Aresti, Karoliina Rebane, Edoardo Charbon, Roberto Baccomi, P. Becht, D. Dannheim, M. D. Buckland, M. Šuljić, Vittorio Di Trapani, G. Aglieri Rinella, P. Švihra, A. Junique, N. Apadula, Jory Sonneveld, F. Piro, F. Křížek, M. Mager, Isabella Sanna, F. Carnesecchi, P. Camerini, S. Masciocchi, Jacob Bastiaan van Beelen, Magdalena Münker, H. Hillemanns, M. Antonelli, F. Reidt, N. Tiltmann, G. Contin, Marius Wilm Menzel, Mirella Dimitrova Vassilev, S. Beolè, Sanghoon Lim, R. Russo, А. Исаков, S. Senyukov, Valerio Sarritzu, Geun Hee Hong, Minjung Kim, Leonardo Cecconi, E. Buschmann, M. Borri, C. Vernieri, Jan Anton Hasenbichler, Antonello Di Mauro, João de Mélo, Alexandre Rachevski, D. Marras, Alex Kluge
article en

Abstract

The next generation of MAPS for future tracking detectors will have to meet stringent requirements placed on them. One such detector is the ALICE ITS3 that aims to be very light at 0.07 % X/X 0 per layer and have a low power consumption in the active area of 40 mW/cm 2 by implementing wafer-scale MAPS bent into cylindrical half layers. To address these challenging requirements, the ALICE ITS3 project, in conjunction with the CERN EP R&D on monolithic pixel sensors, proposed the Tower Partners Semiconductor Co. 65 nm CMOS process as the starting point for the sensor. After the initial results confirmed the detection efficiency and radiation hardness, the choice of the technology was solidified by demonstrating the feasibility of operating MAPS in low-power consumption regimes, < 50 m W / c m 2 , while maintaining high-quality performance. This was shown through a detailed characterisation of the Digital Pixel Test Structure (DPTS) prototype exposed to X-rays and ionising beams, and the results are presented in this article. Additionally, the sensor was further investigated through studies of the fake-hit rate, the linearity of the front-end in the range 1.7–28 keV, the performance after ionising irradiation, and the detection efficiency of inclined tracks in the range 0–45°.

Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated EquipmentVol. 1083
University of Trieste (IT), Lawrence Berkeley National Laboratory (US), Universität Hamburg (DE), University of Cagliari (IT), Heidelberg University (DE), University of Münster (DE), Daresbury Laboratory (GB), Institut Pluridisciplinaire Hubert Curien (FR), Central China Normal University (CN), Istituto Nazionale di Fisica Nucleare, Sezione di Torino (IT), Istituto Nazionale di Fisica Nucleare, Sezione di Cagliari (IT), Istituto Nazionale di Fisica Nucleare, Sezione di Trieste (IT), École Polytechnique Fédérale de Lausanne (CH), University of Turin (IT), European Organization for Nuclear Research (CH)
Openalex Percentile: Top 72%
Integrated Circuits and Semiconductor Failure Analysis
DOIOpen Access PDFOpenAlex
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