Spike-FlexiCAS: RISC-V Processor Simulator Supporting Flexible Cache Architecture Configuration

Cache simulators are indispensable tools for exploring cache architectures and researching cache side channels. Spike, the standard implementation of the RISC-V instruction set, offers a comprehensive environment for RISC-V-based cache research. However, its cache model suffers from limitations, such as low simulation granularity and notable discrepancies with the cache structures of real processors. To address these limitations, this paper introduces the FlexiCAS (flexible cache architecture simulator), a modified and extended version of Spike's cache model. The modified simulator, referred to as Spike-FlexiCAS, supports a wide range of cache architectures with flexible configuration and easy extensibility. It enables arbitrary combinations of cache features, including coherence protocols and implementation methods. In addition, FlexiCAS can simulate cache behavior independently of Spike. The performance evaluations demonstrate that FlexiCAS significantly outperforms the cache model of ZSim, the fastest execution-driven simulator available.