An 8.1-µW 12-bit Non-Binary Self-Clocked SAR-ADC in 130 nm Open-Source PDK

A self-clocked 12-bit non-binary fully differential SAR-ADC, designed using open-source circuit design tools and the open-source SKY130 PDK, is presented. Including a digital wrapper block for configuration and serial readout the layout size is 0.214 µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. With a typical sampling rate of 2 kS/s and using OSR = 16 the power consumption has been measured at 8.1 µW (2.3 µW in sleep mode), and the measured SNR, SNDR, and ENOB are 73.9 dB, 71.1 dB, and 11.5 bit, respectively, which makes the ADC suitable for biomedical applications. The maximum sampling frequency, which was limited by the digital wrapper and the off-chip data read-out unit, is 180 kS/s where the power consumption reaches 286.9 µW.