eduBOS5: A Case Study in Structured SystemVerilog and PPA Optimization for Resource-Constrained RISC-V FPGA Cores

Open-source RISC-V CPU architectures provide FPGA developers with fine-grained control over resource utilization and performance. This work presents a case study in throughput maximization and PPA (power, performance, area) optimization for a minimal RISC-V core on FPGA, with an emphasis on structured SystemVerilog design practices. We propose a short, single-cycle pipeline architecture targeting resource-constrained deployments and systematically compare its PPA characteristics against similar performance-class implementations. FPGA-specific optimizations, including tailored Register File and ALU configurations, are employed to improve critical path timing and overall throughput. The resulting design, eduBOS5, achieves a 2× increase in DMIPS/MHz while reducing LUT utilization by 24% compared to PicoRV32 on the Gowin LittleBee FPGA. PPA metric scaling over different FPGAs was addressed by porting the design to Xilinx and Lattice devices.