A CMOS Source-Coupled Relaxation Oscillator Achieving Close-in Phase Noise of -72.9 dBc/Hz at a 1 kHz Offset

A modified source-coupled relaxation oscillator with dynamic biasing feedback is presented as a reference clock. The proposed topology achieves a close-in phase noise of -72.9 dBc/Hz at a 1 kHz offset. By suppressing the effective impulse sensitivity function of the tail transistors, the technique significantly reduces flicker noise upconversion into the oscillator’s 1/f<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> phase noise. Experimental results demonstrate a close-in figure of merit improvement of approximately 4 dB over previously reported comparator-based RC relaxation and source-coupled relaxation oscillator designs. Implemented in a 0.35 µm CMOS process, the oscillator operates at 2.65 MHz while consuming only 13.2 µW from a 3 V supply.