Comparison of Low Power Digitally Controlled Ring Oscillator Architectures in 12 nm FinFET

This work presents results of a systematic review of digitally controlled ring oscillators with the focus on low-power consumption. Five different topologies are implemented as standalone blocks and compared with regards to power consumption, chip area, phase noise, rms period jitter and an overall figure of merit. The chosen process node of 12 nm FinFET technology gives timely relevant reference for this type of circuit, applicable to numerous applications. A target frequency of 200 MHz is selected. To ensure a fair comparison, all circuits are designed to achieve this frequency over the full process, voltage, bias current and temperature range. Multiple criteria are defined for the remaining design aspects to analyze the five topologies on equal terms. Pros and cons of the different approaches are considered. The discussion emphasizes the design tradeoffs and gives recommendations for various use cases.