Modeling Location-dependent Random Telegraph Noise for Circuit Simulators

As a result of transistor area reduction due to design requirements and process scaling, it is increasingly likely to observe random telegraph noise (RTN). This can severely impact reliability in modern CMOS circuits. We investigate RTN amplitudes under different measurement configurations and propose a novel RTN model for circuit simulation. It is able to represent the influence of the trap location in the channel and the bias-dependence on the RTN amplitudes, which is achieved by transistor segmentation. The presented simulation results align with the experimental analysis. Our model suggests that the edge effect due to shallow trench isolation (STI) can significantly amplify RTN amplitudes. The bias dependence in the weak inversion, particularly important for the low power circuits, follows the known trends from literature.