Improved Montgomery Modular Multipliers on FPGAs and ASICs

This paper presents the design of an Improved Montgomery Modular Multiplier (MMM) employing three large-integer hybrid recursive Karatsuba multipliers (HRKM) with the base cases replaced by Optimized Schoolbook multipliers (OSBM). This method achieves a single-cycle modular multiplier with significantly reduced resource utilization and latency on FPGAs and ASICs. The proposed design is implemented on a Virtex-6 and Virtex UltraScale+ XCVU9P FPGA platform and synthesized using Synopsys Design Compiler for ASIC implementation. Experimental results on the AMD FPGA platform demonstrate a notable reduction in area-time product (ATP) of 92.766% and 95.130% for an improved 256-bit MMM compared to the best state-of-the-art MMMs on the Virtex-6 and Virtex UltraScale+ XCVU9P FPGA platform. Moreover, results of ASIC implementation on United Microelectronics Corporation (UMC) 65nm technology demonstrate a notable reduction in the power time product (PTP) of 22.173% compared to the best state-of-the-art works.