Graph-Oriented Layout Design for Field-Coupled Nanocomputing via Parallel Multi-Objective Search Space Exploration

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Field-coupled Nanocomputing</i> (FCN) is a post-CMOS paradigm in which information propagates through near-field interactions rather than charge flow, enabling ultra-low-power, high-density logic. Translating netlists into manufacturable, cell-level layouts therefore becomes a pivotal challenge. Existing FCN physical design tools optimize only a single cost metric, typically footprint or runtime. As a result, designers must choose between exponentially slow exact solvers and fast yet area-intensive heuristics. We present the first FCN physical design engine that closes this gap by introducing configurable <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">effort modes</i>. These modes let users trade runtime for solution quality while simultaneously optimizing any discretionary objective, e. g. area, wire segments, crossings, or delay, thereby integrating data from physical simulation and manufacturing constraints. Our open-source implementation, released as part of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Munich Nanotech Toolkit</i>, generates layouts for circuits that defeat state-of-the-art exact solvers. On such benchmarks, it shrinks footprint by an average of 73.07 %, reduces crossings by 19.10 %, and cuts wire segments by 54.47 % relative to a leading heuristic baseline. Even after post-layout optimization of the baseline, our approach still achieves mean gains of 25.99 % in area, 37.82% in crossings, and 25.96% in wire segments. These results establish the proposed engine as a compelling solution for highly optimized, large-scale standard-cell FCN design.