FPGA Implementation of Sparsity Adaptive Atomic Correlation Difference Pursuit Algorithm for Compressed Sensing

The reconstruction of signals using reconstruction algorithms is the most critical step in compressed sensing (CS) theory. In practical application scenarios, the sparsity of the signal is often unknown, which requires reconstruction algorithms to operate under sparsity-adaptive conditions. Existing sparsity adaptive algorithms have various limitations, and no algorithm has demonstrated good reconstruction performance in noisy real-world environments. This article fully considers reconstruction accuracy, robustness, and hardware complexity and proposes a sparsity adaptive atomic correlation difference pursuit (SA-ACDP) algorithm to achieve a balance among reconstruction accuracy, robustness, and hardware complexity. Experimental results show that the SA-ACDP algorithm achieves better reconstruction success rate (SR) compared with the existing sparsity adaptive algorithms and comparable reconstruction SR to existing algorithms with prior sparsity knowledge. It also exhibits better robustness and lower hardware complexity compared to existing algorithms. A hardware architecture applying the SA-ACDP algorithm is designed and implemented on a Virtex UltraScale+ FPGA with matrix dimension <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$= 1024\times 256$</tex-math> </inline-formula>, maximum sparsity <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K_{\max }= 128$</tex-math> </inline-formula>. The proposed architecture achieves a reconstruction signal-to-noise ratio (RSNR) of 35.11 dB for random signals and 28.3 dB for ECG signals, with 18-bits data width and 13-bits fractional width. The maximum clock frequency of the architecture is 200 MHz, enabling reconstruction within <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$231~\mu $</tex-math> </inline-formula>s. The proposed architecture achieves a dynamic power consumption of 2393 mW.