Circuit-level analysis of a novel ternary adder in ternary-enabled graphene nanoribbon FETs technology

Abstract The rapid advancement of artificial intelligence (AI) applications, particularly in edge computing, has exposed the limitations of conventional silicon-based hardware, including excessive power consumption, thermal challenges, and insufficient computational density. These issues are exacerbated by the slowing pace of transistor miniaturization under Moore’s law, necessitating innovative semiconductor technologies. While complementary metal-oxide-semiconductor (CMOS)-based ternary logic implementations exist, their reliance on precise threshold voltage regulation results in high power consumption and larger chip architectures. Emerging technologies like Fin-based FETs, carbon nanotube FETs, and Tunnel FETs also face significant constraints, such as fabrication challenges and inadequate performance for ternary logic. This work addresses these challenges by proposing a graphene nanoribbon field-effect transistor (GNRFET)-based ternary half adder (THA) circuit. Leveraging GNRFET’s superior attributes—such as tunable bandgap properties, high carrier mobility, and precise threshold voltage control—the proposed THA circuit achieves enhanced performance. Simulations at 0.9 V show a 41.5% reduction in delay, a 7.7% decrease in power, and a 52.3% improvement in energy efficiency compared to CNTFET-based counterpart. Additionally, the proposed THA circuit achieves at least a 13.7% lower power consumption and a 6.2% enhancement in energy efficiency over previous GNRFET-based THA designs. To further evaluate performance, a ternary full adder (TFA) was implemented using the proposed THA. The design demonstrates significant enhancements, achieving power reductions of 34.3%–58.5%, energy efficiency improvements of 18.6%–70.2%, and transistor count reductions of 19%–34.7% compared to recent GNRFET-based TFA designs.