Achieving 400 Gbps Single-Flow Throughput with Minimal CPU Core Usage through Optimized DPDK and SmartNIC Implementation

As the volume of digital data continues to grow at an unprecedented rate, efficient data processing and transmission have become fundamental requirements. Advancements in Artificial Intelligence (AI), such as large-scale language model training and multimodal content generation, often demand the dynamic transfer of large datasets from diverse input sources to produce complex outputs. On the other hand, distributed computing also relies heavily on fast, dependable data exchange between computing nodes. These emerging needs underscore the critical importance of high-bandwidth network infrastructure, which forms the backbone of data-intensive workflows and supports the effective operation in High-Performance Computing (HPC) environment. Addressing these challenges is essential to fully realizing the capabilities of modern computer network systems and supporting continued progress in data-intensive domains. Hence, this research focuses on identifying key factors that utilizes the Data Plane Development Kit (DPDK) framework to optimize user-space packet processing. The authors aim to implement a testing environment to achieve 400 Gbps single flow throughput with minimal CPU core usage. The experimental results show that tuning of system parameters can significantly improve the network throughput, providing a use case that satisfies the demands of ultra-high-speed network.