FPGA Network Function Acceleration: A Space Division Multiplexing Approach

FPGA-based SmartNICs are increasingly deployed in cloud and edge data centers to offload cryptography, packet shaping and in-network computing. While recent virtualisation techniques (e.g., SR-IOV) allow multiple tenants to share a single FPGA accelerator, each tenant receives a fixed portion of logic resources and must load a private copy of every required network function. How to improve the resource utilization of FPGA accelerators, meet the stringent service quality constraints of multi-tenants, and provide resource sharing fairness are the main goals of FPGA network function acceleration. We present FPGASDM, a virtualized FPGA resource sharing method based on space division multiplexing. In FPGA-SDM, each tenant is issued a private vFPGA domain realised through SR-IOV queues and DMA engines, while a reconfigurable public service pool hosts the library of packet-processing acceleration function that are loaded on demand via partial reconfiguration.Our moduel show that, under tenant activity levels of $\mathbf{0. 3 - 0. 6}$ and sharing ratios of $0.4-0.7$, the system achieves up to $1.5 \times$ performance improvement over static resource allocation. Moreover, the experimental results confirm that FPGA-SDM achieves line-rate throughput, maintains near-optimal throughput levels under the influence of malicious tenants, and improves average resource utilization up to $49.5 \%$.