Design and Implementation of Embedded Image Processing Chip Based on Lightweight MobileNetV3

Aiming at the contradiction between the accuracy loss caused by model compression and limited hardware resources when lightweight MobileNetV3 is deployed on embedded chips, a dynamic quantization and hardware acceleration collaborative optimization method is proposed. Dynamic bit width allocation is achieved through gradient sensitivity analysis and non-uniform quantization, and precision is improved by combining quantization-aware training; a hardware accelerator based on FPGA (Field Programmable Gate Array) is designed to support real-time dynamic quantization and efficient convolution calculation. Experiments show that this method achieves 92.3% Top-1 accuracy and 20.5 Frames/J energy efficiency on the Xilinx Zynq platform. Compared with TensorFlow Lite, the model compression rate is increased by 23%, and the inference latency is reduced by 41%, providing a new paradigm for edge image processing.