Fully Pipelined High-Speed Implementation of the SM4-GCM Algorithm on FPGA

With the rapid development of big data and 5 G technologies, high-speed communication systems are placing increasingly stringent demands on the performance and adaptability of encryption algorithms. To address the low throughput of traditional SM4—GCM implementations, this paper conducts an in-depth analysis of the algorithm’s structure and proposes an optimized hardware architecture based on FPGA. The 32 round nonlinear iteration of the SM4 algorithm is reduced to 8 rounds, significantly improving computational efficiency. Additionally, by incorporating shift XOR based multiplication and a fast modular reduction method, the proposed design accelerates the SM4-GCM algorithm using fully pipelined and eight-core parallel processing techniques. This achieves a unified balance between high throughput and strong security.