Design and fabrication of a SiC trench MOSFET with multi-step p-type shielding and multiple CSL layers

This study presents the design and fabrication of a SiC trench MOSFET featuring a multi-step p-type shielding region (P+SLD) and multiple current spreading layers (CSL) (MPC-TMOS). Compared with the conventional SiC trench MOSFET with single P+SLD (P-TMOS), the proposed structure employs a self-aligned process to form the multi-step P+SLD without additional masks. Therefore, there are only minor changes in the fabrication process and cost does not increase significantly. Numerical 2D-simulation has been conducted to compare the electrical characteristics of the MPC-TMOS and P-TMOS. The results indicate comparable specific on-resistance (R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</inf>) and breakdown voltage (BV) for both structures. However, the MPC-TMOS demonstrates superior gate oxide reliability, with a peak electric field (E<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox,peak</inf>) of 2.89 MV/cm at 1200 V drain voltage—a 12.69% reduction compared to the 3.31 MV/cm observed in the P-TMOS. Experimental tests of the MPC-TMOS samples show a BV of 1700 V and an on-state resistance (R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf>) of 50.7 mΩ. Additionally, the influence of key structural parameters is analyzed, offering insights for further device optimization.