Diagnostic Test Compaction of Functional Test Sequences

Functional test sequences are applied to detect defects that escape scan-based tests. The application of a functional test sequence requires a large number of clock cycles. Therefore, test compaction is applied to reduce the number of clock cycles without losing fault coverage. When a functional test sequence is used for logic diagnosis, it is important to ensure that test compaction does not eliminate useful diagnostic information. This article addresses this problem for the first time by describing a new test compaction procedure for functional test sequences. The ability of a sequence to support logic diagnosis is assessed by performing diagnostic fault simulation. To limit the computational effort, the test compaction procedure incorporates a dynamically changing parameter that limits the number of times diagnostic fault simulation is carried out during compaction. Experimental results for benchmark circuits demonstrate the effectiveness of the procedure, and the use of observation points.

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Publication Details

Journal
IEEE Access
Published
2025-01-01
DOI
https://doi.org/10.1109/access.2025.3618719
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
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article

Diagnostic Test Compaction of Functional Test Sequences

Irith Pomeranz
IEEE Access
VLSI and Analog Circuit Testing
article

Diagnostic Test Compaction of Functional Test Sequences

Irith Pomeranz
article en

Abstract

Functional test sequences are applied to detect defects that escape scan-based tests. The application of a functional test sequence requires a large number of clock cycles. Therefore, test compaction is applied to reduce the number of clock cycles without losing fault coverage. When a functional test sequence is used for logic diagnosis, it is important to ensure that test compaction does not eliminate useful diagnostic information. This article addresses this problem for the first time by describing a new test compaction procedure for functional test sequences. The ability of a sequence to support logic diagnosis is assessed by performing diagnostic fault simulation. To limit the computational effort, the test compaction procedure incorporates a dynamically changing parameter that limits the number of times diagnostic fault simulation is carried out during compaction. Experimental results for benchmark circuits demonstrate the effectiveness of the procedure, and the use of observation points.

IEEE AccessVol. 13
Purdue University West Lafayette (US)
Openalex Percentile: Top 70%
VLSI and Analog Circuit Testing
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Diagnostic Test Compaction of Functional Test Sequences — Irith Pomeranz · IEEE Access (2025) | TGRS Research Map | TGRS