Degradation of Planar-Gate SiC MOSFETs Under Repetitive Short-Circuit Stress in Different Gate Bias

The lifetime and degradation of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have garnered increasing attention from device users and power electronics system designers. This work establishes an experimental platform for repetitive short-circuit tests of SiC MOSFETs. Under varying gate voltage (U<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf>) conditions, comprehensive experimental investigations are conducted on the degradation characteristics of static parameters under repetitive short-circuit stresses, including zero gate voltage drain current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSS</inf>), threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf>), on-state resistance (R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS(on)</inf>), and breakdown voltage (BV), and gate-source leakage current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSS</inf>). The experimental results reveal the degradation trends and patterns of these parameters as the number of short-circuit pulses increases.