Design and Demonstration of a Novel SiC Trench MOSFET with Periodically Grounded P Shield Island Based on Secondary Epitaxy Process

This paper proposes a novel silicon carbide (SiC) trench MOSFET with periodically grounded P shield islands (SiC PSI-MOS) based on a secondary epitaxy process. The proposed SiC PSI-MOS structure utilizes a patterned P shield island formed through etching, ion implantation, and secondary epitaxy, enabling deeper shielding with lower energy implantation while maintaining gate oxide reliability. In the blocking state, the P shield region and P shield island effectively shield the drain potential, reducing the gate oxide electric field to a safe level (1.07 MV/cm at 1200 V). In the on-state, the drift between the P shield and the island creates additional current paths, lowering specific on-resistance (4.9 mΩ·cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at a 7.5 μm cell pitch). In addition, a feasible fabrication process is demonstrated, with experimental results confirming the device’s output and transfer characteristics. The SiC PSI-MOS offers an optimized trade-off between gate oxide reliability and conduction performance.

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Published
2025-08-15
DOI
https://doi.org/10.1109/wipda-asia63772.2025.11184093
Primary Topic
Silicon Carbide Semiconductor Technologies
Type
article
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article

Design and Demonstration of a Novel SiC Trench MOSFET with Periodically Grounded P Shield Island Based on Secondary Epitaxy Process

Yangyang Wu, Fei Guo, Wei Chen, Zhijie Cheng et al.
Silicon Carbide Semiconductor Technologies
article

Design and Demonstration of a Novel SiC Trench MOSFET with Periodically Grounded P Shield Island Based on Secondary Epitaxy Process

Yangyang Wu, Fei Guo, Wei Chen, Zhijie Cheng, Guoqing Xin, Kuan Wang, Jun Yuan, Zhiqiang Wang, Rong Zhang
article en

Abstract

This paper proposes a novel silicon carbide (SiC) trench MOSFET with periodically grounded P shield islands (SiC PSI-MOS) based on a secondary epitaxy process. The proposed SiC PSI-MOS structure utilizes a patterned P shield island formed through etching, ion implantation, and secondary epitaxy, enabling deeper shielding with lower energy implantation while maintaining gate oxide reliability. In the blocking state, the P shield region and P shield island effectively shield the drain potential, reducing the gate oxide electric field to a safe level (1.07 MV/cm at 1200 V). In the on-state, the drift between the P shield and the island creates additional current paths, lowering specific on-resistance (4.9 mΩ·cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at a 7.5 μm cell pitch). In addition, a feasible fabrication process is demonstrated, with experimental results confirming the device’s output and transfer characteristics. The SiC PSI-MOS offers an optimized trade-off between gate oxide reliability and conduction performance.

Huazhong University of Science and Technology (CN)
Openalex Percentile: Top 73%
Silicon Carbide Semiconductor Technologies
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