The Establishment of Quasi-3D TCAD Simulation for Bipolar Degradation Occurs in SiC MOSFET Body Diode

Bipolar degradation (BD) in SiC MOSFETs is one of the reliability issues that limit the long-term operation of the devices. Under bipolar conduction conditions, as the Stacking Faults (SF) in the epitaxial layer expanding, the device resistance and body diode voltage drop increase significantly. This paper determines the correlation between the degree of electrical parameter degradation and the expansion of the SF area through constant current electrical stress loading and Photoluminescence (PL) defect distribution characterization. In addition, by introducing a 0.75nm-thick 3C-SiC layer at a 4° angle and controlling its expansion length, a quasi-3D simulation to describe the BD process was constructed for the first time. The changes in various parameters in the epitaxial layer obtained from the simulation were consistent with existing research conclusions, and the simulated body diode V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</inf> shift achieves a high degree of consistency with the actual measurements. This work contributes to the study of the mechanism of bipolar degradation in SiC and the reliability assessment of devices under long-term stress in applications.