Multi-Objective Optimization for Three-Level Power Module Based on Electro-Thermal Co-Design

Due to the characteristics of multi-chip, multi-commutation loops, and multiple operating modes in three-level power modules, there often exists a design conflict between the loop parasitic inductance and the junction temperature of the chips, making it challenging to simultaneously achieve low parasitic inductance for different loops and low junction temperature for chips under various operating modes. To address this issue, this paper proposes a multi-objective optimization design method for three-level power modules based on electro-thermal co-design, targeting loop parasitic inductance (L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">loop</inf>), chip junction temperature (T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf>), and thermal stress. By establishing models for multi-loop parasitic inductance and chip junction temperature under different operating modes, this method explores the influence of chip layout on L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">loop</inf> for different loops, under various modes, and thermal stress through electro-thermal co-simulation. Furthermore, guided by the principle of trade-off design, a three-level power module with balanced electro-thermal performance is designed. Based on a self-developed packaging and interconnection platform, the designed power module is fabricated. Electrical-Thermal characterization and reliability tests are conducted on the assembled module. The results demonstrate that the proposed design method significantly improves the comprehensive performance of the module.