UIS Ruggedness of Si/SiC Hybrid Switches

Although the hybrid switch consisting of high power Si IGBT and low power SiC MOSFET achieves reduction of losses and cost, there is a severe concern of its UIS capability under single-pulse mode. The limiting factors and in-depth failure mechanism of UIS capability have not been comprehensively studied yet. In this article, we investigated UIS of the Si/SiC hybrid switch and its internal devices with various sizing ratios and gate control patterns. It is observed that the avalanche current of the hybrid device is predominantly sustained by the SiC MOSFET and increases with the increasing SiC MOSFET sizing during the avalanche process. Furthermore, the influence of gate control patterns is also analyzed. Optimizing the gate turn-off delay period in SiC MOSFET enhances avalanche ruggedness characteristics within hybrid switch. Finally, the UIS failure mechanism of the hybrid switch is discussed.