Gate-Source Voltage Oscillation of Multi-chip SiC Power Modules Considering Differential Gate Resistance

This study investigates the application and performance characteristics of Silicon carbide (SiC) power modules, which are widely utilized in industrial settings due to their high power density and reliability. However, gate oscillations frequently manifest during the turn-off phase, particularly due to circuit asymmetry and parasitic parameters associated with the chips. To address this issue, this research establishes a dynamic model of the multi-chip turn-off process, aimed at identifying the primary sources of oscillations. The study systematically analyzes the effects of individual gate resistance and differential gate resistance, and their influence on oscillations under conditions of parasitic inductance imbalance. Experimental results demonstrate the effectiveness of the proposed approach, with further validation conducted through double-pulse testing.