Dry Oxidation and SiO₂ Deposition Strategies for High-Performance Gate Dielectrics in 3.3 kV SiC Power MOSFETs

This study presents the static electrical characteristics of a 3300 V silicon carbide planar MOSFET employing an optimized JFET region design. Devices with dry oxide and SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> deposited by low pressure chemical vapor deposition followed by NO annealing were utilized in this study. The MOSFETs with SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> deposition as the gate dielectric achieved a mobility of 20 cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>/Vs, representing an enhancement over the 16 cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>/Vs achieved for the dry oxide, albeit with a thicker thickness. With the gate voltage fixed at 20 V, a specific on-resistance of 21 mΩcm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was measured, and the fabricated MOSFETs demonstrated a drain voltage of 4375 V and a leakage current of 1 mA without exhibiting any avalanche breakdown.