Analysis of Influencing Factors on the Thermal Performance of SiC Multi-Chip Parallel Packaging Structure

With the advancement of chip and packaging technology, silicon carbide device voltage and current levels, power density, operating junction temperature and other performance indicators are also increased accordingly, the device packaging, especially packaging heat dissipation poses a higher challenge. Device packaging miniaturization, integration so that the device heat flow density increased significantly, research shows that more than 50% of the power device failure is caused by the high temperature, and the temperature rises 10℃, the device failure rate will be nearly doubled. Especially for multi-chip parallel package devices, the package internal chip thermal coupling leads to high chip temperature and temperature distribution is extremely uneven, exacerbating the formation of hot spots. Silicon carbide material itself has the ability to withstand high temperatures, but due to the existing silicon carbide device packaging is still using the traditional silicon-based device packaging route, so that the existing silicon carbide power devices can not give full play to its potential. In order to enhance the high-temperature resistance of silicon carbide devices, the use of high thermal conductivity packaging materials, optimize the thermal resistance at the packaging level and improve the external heat dissipation have become two hot topics in the research of silicon carbide device packaging, and the heat dissipation problem of silicon carbide devices has become one of the key technical bottlenecks affecting the operational reliability of the devices. Based on the above problems, this paper firstly establishes a three-dimensional heat conduction model of silicon carbide devices based on Fourier's law of thermal conductivity. Secondly, based on the finite element numerical method, the thermal performance of silicon carbide multi-chip parallel device packaging is studied, and the influence of layout parameters such as the number of chips and spacing, the type of encapsulation material and parameters on the thermal performance of the device packaging is obtained, so as to clarify the optimization direction of the thermal performance of the device at the encapsulation level. Finally, the correctness of the simulation results is verified based on experimental tests. The results of the study can provide a theoretical basis for the design of silicon carbide device packaging layout, packaging material selection and performance enhancement.