The Method for Chip Sorting Based on SiC MOSFET Parameters for Parallel Current Sharing under a Symmetrical Layout

Parallel connection of multiple SiC MOSFET chips is a crucial approach to meeting the demands of higher-power applications. However, due to variations in chip parameters, imbalanced current distribution occurs among the parallel devices. This paper systematically investigates current balancing methods for parallel SiC MOSFETs to address this issue. First, the static parameters of 30 single-chip SiC MOSFET devices were tested, and a statistical analysis was conducted to evaluate the parameter dispersion affecting parallel current distribution. Then, the Pearson correlation coefficients between the gate-source voltage and transconductance under different current levels were established. The gate-source voltage at which the Pearson correlation coefficient reaches -0.7 was defined as the current-balancing voltage, based on which a chip sorting criterion was proposed. Subsequently, chip selection was optimized using the current-balancing voltage as the sorting indicator. Finally, an experimental platform for multiple discrete devices in parallel was constructed to verify the effectiveness of the proposed method.