Investigation on Surge Current Failure in 1200V SiC MOSFETs with Varied Gate Biases in the Third Quadrant

In this work, third-quadrant I-V characteristics and surge current tests are conducted on three commercial SiC MOSFETs (Device A, B and C) under varying gate bias conditions (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf>). Experimental results indicate that under a -5V gate bias, the maximum surge current the device can tolerate decreases compared to operation at 0V and +15V gate biases. This suggests that for high-current devices, both 0V and +15V gate biases enhance surge reliability. The findings highlight the importance of gate bias optimization in improving surge tolerance, emphasizing that certain gate voltages significantly contribute to better surge resilience in high-power devices. Decapsulation analysis identifies localized metal layer melting on the chip surface as the primary failure mechanism at V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf>=0V. The findings highlight gate-bias-dependent electro-thermal dynamics as a factor in SiC MOSFET surge reliability optimization.