Modeling of Static Current Sharing of Direct-Paralleled 1.7kV 800A SiC Power Modules

High-power applications often require paralleling of power modules. Due to lower on-resistance and parasitic inductance than that of silicon IGBTs, SiC power module paralleling is found to be more challenging. This paper analyzes the impedance characteristics of three paralleled SiC modules and develops a time-domain model to quantify the parasitic’s impact on current distribution. Double-pulse tests verified the model and demonstrated the parallel operation of three SiC modules with satisfactory current sharing. By optimizing power loop impedance, current-sharing deviation is reduced to less than 4% at 1100V/1200A switching conditions.