SiC Power Module with Staggered Terminals Layout Design to Reduce Parasitic Inductance

This paper introduces a novel staggered terminal layout for SiC MOSFET multi-chip power modules. The proposed layout reduces parasitic inductance by canceling inductance within the power loop and between power terminals, while also enhancing current balance through an axisymmetric layout. The parasitic inductance of the proposed SiC power module is approximately 3.85 nH. Compared to commercial counterpart with the same current rating, the parasitic inductance is reduced by 4.26 nH. Furthermore, the drain voltage overshoot in the proposed power module is reduced by approximately 23 V, and the switching loss is lowered by nearly 1020 μJ under test conditions of 600 V/100 A.