Research on Threshold Voltage Instability of SiC MOSFETs at High Temperature

Silicon carbide MOSFETs have a promising future in electric vehicles, aerospace and other fields due to their high-temperature resistance and low-loss characteristics, but their high-temperature reliability is severely constrained by threshold voltage instability. In this paper, in response to the shortcomings of existing studies at ultra-high temperatures (150~275°C) and wide gate voltage ranges, a bias temperature instability (BTI) experimental platform is constructed to systematically investigate the effects of gate bias and high temperature on the threshold voltage instability of silicon carbide MOSFETs. It is found that: ∆V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> is negatively correlated with temperature in the range of 150~175°C, and positively correlated with temperature in the range of 175~275°C This is due to the competition between the bidirectional tunneling process of charges in the traps and the thermal activation process of the traps in the different temperature intervals; under negative gate bias (NBTI), the trap-assisted tunnelling (TAT) is triggered by the high field strength and the high temperature can activate the deep mobile ions in the oxide layer, leading to an anomalous temperature dependence of the threshold voltage drift. The dominant roles of the host trap (forbidden band mid/valence band) and the donor trap (conduction band) on the drift direction are further verified by Sentaurus TCAD simulations. In this study, the synergistic degradation path between gate voltage and temperature at ultra-high temperatures is clarified for the first time, and the application design guideline based on the temperature turning point is proposed, which provides theoretical support and experimental basis for the optimization of the reliability of silicon carbide devices under extreme operating conditions.