Study on Influencing Factors and Mechanisms of Single-Event Gate Rupture in SiC STP-MOSFETs

This paper investigates the impact factors, mechanism, and mitigation strategies of single-event gate rupture (SEGR) in Shallow Trench-Planar Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors (SiC STP-MOSFETs), which are effective in reducing specific on-resistance. Compared with conventional planar gate MOSFETs (Con-MOSFETs), STP-MOSFETs exhibit a 17.2% reduction in specific on-resistance. However, it has been observed that STP- MOSFETs are more susceptible to SEGR. Specifically, at a position 0.4 μm away from the cell center and under 90° vertical incidence, the hole accumulation effect at the bottom of the gate oxide layer is most pronounced. When the N-drift region is completely penetrated by heavy ions and the linear energy transfer (LET) value is 0.1 pC/μm, the SEGR threshold voltage of STP-MOSFETs is only 48 V, which is 10.4% lower than that of conventional structures. After reinforcement with high-k dielectric HfO?, the SEGR threshold voltage is increased by 165%.