Substrate Coupling Considerations for Monolithic Integration of High-Voltage Power Transistors with Low-Voltage Devices and Circuits in GaN-on-Si Technology

The device area dependence of substrate coupling in GaN-on-Si technology is investigated in situations of integrating a high-voltage large-sized transistor on the same chip. It is found by computational electromagnetic (EM) investigation that |S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</inf>| as a measure of the EM coupling increases minimally by ≈7.7 dB/decade or less, when the device area increases by size expansion along the separation direction. This implies that |S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</inf>| at 30 MHz would increase by at least 31 dB from -77 dB (for 2×2 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area) to -46 dB (or -25 dB in the worst case), when a typical power transistor of 40-mm channel width is placed at 300 μm away from a device that is 10 thousand times smaller in area.