Deadtime Compensation Method for Synchronous Optimal Pulsewidth Modulation

Synchronous optimal pulse-width modulation (SOPWM) techniques are widely recognized for their superior total harmonic distortion (THD) performance compared to other PWM techniques. However, their effectiveness is highly reliant on the precise switching of semiconductor devices in the voltage source inverters (VSIs). In practice, VSIs require a deadtime between the switching of upper and lower semiconductor switches to prevent short-circuiting the DC-link, which introduces a non-negligible difference between the optimal pulse pattern (OPP) and the actual output voltage waveforms. These errors result in increased THD as well as magnitude and phase shift errors in the output voltage, leading to a noticeable deterioration in the overall performance in SOPWM-controlled VSIs. To address these issues, this paper presents a novel deadtime compensation method specifically designed for SOPWM techniques used in VSIs. The proposed method manipulates the reference voltage angle in real-time, modifying the OPP to eliminate errors caused by the deadtime, turn-on and turn-off delays of switches. Simulation and experimental results demonstrate that the proposed method substantially mitigates the adverse effects of deadtime on SOPWM-controlled two-level VSIs, ensuring that the output voltage waveforms closely match the expected output voltage waveform. Experimental results show up to 14% lower current THD and up to 8% lower voltage THD compared to SOPWM without compensation. Furthermore, the proposed method is versatile, offering compatibility with both open-loop and closed-loop control strategies, thereby enhancing the reliability and efficiency of SOPWM across a wide range of applications.

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Publication Details

Journal
IEEE Journal of Emerging and Selected Topics in Industrial Electronics
Published
2025-10-03
DOI
https://doi.org/10.1109/jestie.2025.3617868
Primary Topic
Embedded Systems and FPGA Design
Type
article
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article

Deadtime Compensation Method for Synchronous Optimal Pulsewidth Modulation

Giorgio Pietrini, Battur Batkhishig, Yash Veer Singh, Rohit Baranwal et al.
IEEE Journal of Emerging and Selected Topics in Industrial Electronics
Embedded Systems and FPGA Design
article

Deadtime Compensation Method for Synchronous Optimal Pulsewidth Modulation

Giorgio Pietrini, Battur Batkhishig, Yash Veer Singh, Rohit Baranwal, Ali Emadi, Pedro F. C. Gonçalves, Babak Nahid‐Mobarakeh
article en

Abstract

Synchronous optimal pulse-width modulation (SOPWM) techniques are widely recognized for their superior total harmonic distortion (THD) performance compared to other PWM techniques. However, their effectiveness is highly reliant on the precise switching of semiconductor devices in the voltage source inverters (VSIs). In practice, VSIs require a deadtime between the switching of upper and lower semiconductor switches to prevent short-circuiting the DC-link, which introduces a non-negligible difference between the optimal pulse pattern (OPP) and the actual output voltage waveforms. These errors result in increased THD as well as magnitude and phase shift errors in the output voltage, leading to a noticeable deterioration in the overall performance in SOPWM-controlled VSIs. To address these issues, this paper presents a novel deadtime compensation method specifically designed for SOPWM techniques used in VSIs. The proposed method manipulates the reference voltage angle in real-time, modifying the OPP to eliminate errors caused by the deadtime, turn-on and turn-off delays of switches. Simulation and experimental results demonstrate that the proposed method substantially mitigates the adverse effects of deadtime on SOPWM-controlled two-level VSIs, ensuring that the output voltage waveforms closely match the expected output voltage waveform. Experimental results show up to 14% lower current THD and up to 8% lower voltage THD compared to SOPWM without compensation. Furthermore, the proposed method is versatile, offering compatibility with both open-loop and closed-loop control strategies, thereby enhancing the reliability and efficiency of SOPWM across a wide range of applications.

IEEE Journal of Emerging and Selected Topics in Industrial ElectronicsVol. 7(1)
Eaton (United States) (US), Vestas (Denmark) (DK), McMaster University (CA)
Openalex Percentile: Top 66%
Embedded Systems and FPGA Design
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