A Single Transistor Memristor Emulator-Based Neuron Circuit

This article presents a memristor emulator circuit, the first to employ only a single MOSFET and a capacitor, achieving high frequency operation up to 50 MHz. The MOSFET operates in saturation with its gate and drain shorted, functioning as a current source to charge the capacitor and emulate memristive behavior. The design achieves low transient power consumption of 33 µW (NMOS) and 28 µW (PMOS) using 180 nm SCL technology in Cadence Virtuoso. Extensive analyses including frequency, transient, non-volatility performance, and process variation studies were performed and validated through pre- and post-layout simulations. Experimental verification using off-the-shelf components confirmed its practicality. As a key application, a spiking neuron circuit utilizing the emulator demonstrated biologically inspired spiking behavior, featuring a compact layout (66.10 µm × 95.80 µm), energy per spike of 4.07 pJ, and power consumption of 7.31 µW, underscoring its promise for low power neuromorphic computing.

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Publication Details

Published
2025-10-03
DOI
https://doi.org/10.36227/techrxiv.175952493.32124919/v1
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.00

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article

A Single Transistor Memristor Emulator-Based Neuron Circuit

Rajeev Kumar Ranjan, Rahul Ranjan, Basit Shafat Makhdoomi, Arun Kalakola
Advanced Memory and Neural Computing
article

A Single Transistor Memristor Emulator-Based Neuron Circuit

Rajeev Kumar Ranjan, Rahul Ranjan, Basit Shafat Makhdoomi, Arun Kalakola
article en

Abstract

This article presents a memristor emulator circuit, the first to employ only a single MOSFET and a capacitor, achieving high frequency operation up to 50 MHz. The MOSFET operates in saturation with its gate and drain shorted, functioning as a current source to charge the capacitor and emulate memristive behavior. The design achieves low transient power consumption of 33 µW (NMOS) and 28 µW (PMOS) using 180 nm SCL technology in Cadence Virtuoso. Extensive analyses including frequency, transient, non-volatility performance, and process variation studies were performed and validated through pre- and post-layout simulations. Experimental verification using off-the-shelf components confirmed its practicality. As a key application, a spiking neuron circuit utilizing the emulator demonstrated biologically inspired spiking behavior, featuring a compact layout (66.10 µm × 95.80 µm), energy per spike of 4.07 pJ, and power consumption of 7.31 µW, underscoring its promise for low power neuromorphic computing.

Ministry of Electronics and Information technology, Indian Institute of Technology (Indian School of Mines), Dhanbad
Openalex Percentile: Top 73%
Advanced Memory and Neural Computing
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