Engineering the ferroelectric polarization to optimize the GIDL and negative output conductance in negative capacitance FET

This paper presents the optimization of the gate induced drain leakage (GIDL) and negative output conductance (NOC) effect in ferroelectric negative capacitance (NC) FET by engineering the polarization of ferroelectric. The improvement in NOC and GIDL is presented with reworked polarization and hence the channel potential at the drain side through gate workfunction modulation. An NC SOI device structure is considered in this work, as this study is intended to investigate the proposed optimization technique. With the metal length ratios of 1:1 and 1:2, the proposed structure offered an enhanced ferroelectric polarization via surface potential amplification at the drain end of the channel. The onset of NOC is delayed by 0.21 V with an improved GIDL current of 3.18 nA and a minimum subthreshold swing of 33.45 mV/decade for the metal length ratio of 1:1.