Optimized NCFET-based approximate multiplier for energy-aware image applications

Applications for multimedia at high speeds has driven the need for error-resilient circuits that trade-off with accuracy while enhancing performance. However, the challenges posed by CMOS scaling are significant, and they have steered VLSI engineers towards exploring beyond-CMOS technology, Negative Capacitance FETs (NCFETs) with a sense of urgency. Enhancing the performance of multipliers is essential, as they are key components in various applications, including image processing and advanced learning algorithms. With the benefits of approximate computing for reducing the energy consumption of applications where exactness is not a requirement while simplifying the design of the circuits. The work here develops highly efficient approximate 4:2 compressors and multiplier circuits, representing core elements in approximate computing systems. This study introduces an innovative 8*8 approximate multiplier based on a 45nm Verilog-A NCFET technology model. It features a cutting-edge 4:2 compressor engineered for exceptional energy efficiency. By operating at a remarkably low voltage of 0.5V, the multiplier significantly reduces power consumption and energy usage compared to existing architectures. Our simulation results are compelling: the 4:2 compressor consumes just 0.122aJ of energy with NCFET technology, far outperforming alternatives like 31.67aJ, 10.49aJ, 172.75aJ in 45nm CMOS technology at 1V, which the proposed work outperforms them despite operating at half the voltage. Moreover, we have successfully realised an 8*8 approximate multiplier incorporating these compressors for image multiplication using MATLAB. The proposed design shows substantial improvements in PSNR and MSSIM and surpasses leading approximate accuracy and energy efficiency multipliers.