Electrostatics, scaling, and variability in stacked graphene nanoribbon FETs without metal interlayers

We present a self-consistent quantum transport simulation of vertically stacked graphene nanoribbon gate-all-around (GAA) field-effect transistors (FETs) without metal interlayers, focusing on the interplay between electrostatics, scaling behavior, and device variability. Removing gate metal interlayers from the conventional GAA structure simplifies the fabrication process but introduces strong electrostatic screening between neighboring graphene ribbons. Our simulations show that increasing inter-ribbon spacing and scaling the sidewall gate oxide substantially improve gate control, enhance the ON/OFF current ratio (ION/IOFF), and suppress short-channel effects, particularly in multi-ribbon configurations. Specifically, when the inter-ribbon spacing exceeds 7 nm, gate efficiency improves significantly, enabling a 3-ribbon device to outperform a monolayer device in ION/IOFF, while only slightly compromising subthreshold swing (SS). Lateral oxide optimization further enhances performance, with ION/IOFF increased by 186% and SS reduced by 27% for the 3-ribbon device when the sidewall oxide is scaled from 4 to 1 nm. Co-optimizing oxide thickness and inter-ribbon spacing also leads to a 36% reduction in SS and a 49% reduction in drain-induced barrier lowering at an 8 nm channel length, compared to an unoptimized 3-ribbon device. Finally, a statistical study with 400 devices of randomly varied geometry demonstrates that these optimizations improve electrostatic robustness and significantly suppress device-to-device variability under realistic misalignment conditions, establishing practical design principles for scalable, low-variability, metal-interlayer-free GAA nanosheet FETs for future electronic applications.