Interleaved ADC: Analysis of Accuracy and Methods for Improving It

Introduction. In many modern applied tasks, it`s necessary to measure fast-moving processes or high-frequency signals, while ensuring a wide range and high bandwidth of the measurement channel. This can be achieved through the usage of high-speed analog-to-digital converters (ADCs), what is not always feasible or rational for a number of systems, in particular modern information and communication technologies, surveillance and radar systems, industrial measurement systems, Internet of Things (IoT) tools and wireless sensor networks, where the main requirements are a significant increase in the sampling frequency with a guarantee of high accuracy of signal acquiring. One of the approaches to solve this task is to use several ADCs in the measurement channel, which work parallel in interleave mode and form the combined code at the output. Theoretically, by shifting the triggering signals of each of these convertors, it is possible to increase the sampling frequency of the input signal as many times as number of ADCs in the interleave mode are connected to the measurement channel after the sensor. The purpose of the work is to increase the accuracy of ADCs in the interleave mode based on the analysis of errors, caused by the action of influential factors, and methods for minimizing these errors. The usage of these methods makes it possible to increase the throughput of the measurement channel by using several ADCs in the interleave mode without increasing the conversion error and overloading individual ADCs. Conclusions. Interleaved ADCs allow reaching greater throughput compared to standard converters. Using two or more standard ADCs in interleaved mode allows for multiple increase in throughput. However, the accuracy of interleaved ADCs is affected by the mismatch between the parameters of individual converters and their components. The parameters of interleaved ADCs have been sufficiently detailed considered in the frequency domain. However, this analysis primarily considers frequency disturbances that appear from differences in the formation of numerical samples by each converter. The amplitude errors of these samples are usually considered due to differences in bias currents and bias voltages between individual ADCs in interleaved mode. However, the amplitude errors due to differences in frequency response, parameters of sample and hold amplifiers remain outside the attention of developers. The impact of these discrepancies on the overall accuracy of interleaved ADCs and methods for minimizing them are discussed in this publication. Keywords: analog-to-digital converter, interleaved ADCs, sample-and-hold amplifier, measurement channel, minimization of conversion errors.