Stable hysteresis-free and ultrahigh photoresponsivity top-gated BP transistors with PMMA/Al ₂ O ₃ /two-dimensional perovskite heterostructure dielectric

To be compatible with current integrated circuit technology, top-gated black phosphorus field-effect transistors (BP FETs) that can individually control the switches of each device are necessary. However, the trapped charge at the gate dielectric layer tends to cause large hysteresis, which severely affects the stability and reliability of logic devices, sensors, and driver circuits. Here, a PMMA/Al₂O₃/two-dimensional perovskite (2D PVK) heterostructure gate dielectric layer is proposed for top-gated BP transistors. The PMMA is used here both as a buffer layer to avoid damage from deposited Al₂O₃ and as a water/oxygen barrier encapsulation layer. Owing to the hysteresis caused by ion migration in 2D PVK counteracting the hysteresis caused by the charge trap in the Al₂O₃ layer, the hysteresis window of the device is almost negligible. With the heterostructure dielectric, the top-gated BP FETs exhibit excellent stability in different scan speeds, bias stress stability, and multi-cycle tests. In addition, due to the strong light absorption properties of the 2D PVK, the device demonstrates an ultra-high photoresponsivity of 1.5 × 10⁷ A W^-1 and an excellent detectivity of 10¹² Jones.