Test pattern optimization scheme based on Hybrid Ant Colony Optimization

The trend toward device miniaturization has made digital circuit testing both essential and increasingly complex. To achieve complete fault coverage, a large number of test patterns are applied, which leads to increased switching activity due to larger number of transitions between consecutive patterns. This rise in switching activity significantly elevates power consumption during testing. Therefore, minimizing transitions between test patterns is crucial for reducing test power. Optimizing test patterns by reducing their count and reordering them is an effective approach to lower switching activity. In this paper, Hybrid Ant Colony Optimization technique is proposed to reduce power consumption during sequential circuit testing. This approach integrates traditional Ant Colony Optimization with Kullback-Leibler divergence and Prim's algorithm. The combination of Ant Colony Optimization and Kullback-Leibler divergence helps in reducing the number of test patterns based on the probability of ant traversal. The resulting patterns are then reordered using Prim's algorithm to minimize transitions between them. Experimental evaluation reveals that the proposed methodology achieves a 71.60% reduction in transition count over the conventional Ant Colony Optimization algorithm on smaller ISCAS'89 benchmark circuits. Furthermore, it attains an average power reduction of 57.48% when compared to test patterns generated using a Linear Feedback Shift Register (LFSR), highlighting its effectiveness in low-power VLSI testing.