An 8‐Bit 32‐GS/s Time‐Interleaved Two‐Step Flash ADC With Common‐Mode Compensated Buffer in 40‐nm CMOS

ABSTRACT To address the ultrahigh sampling rate requirements of analog‐to‐digital converters (ADCs) in high‐speed signal acquisition systems, this paper proposes a multichannel time‐interleaved (TI) ADC architecture based on 40‐nm CMOS technology. This 8‐bit 32‐GS/s TI ADC employs a two‐stage TI architecture, achieving the ultrahigh sampling rate by using multiphase clocks to control 16 sub‐ADCs for alternating sampling. The input buffer utilizes a push–pull configuration capable of isolating the input signal's common mode, while the output buffer adopts a PMOS source follower structure with common‐mode compensation. This ensures the necessary linearity and bandwidth for the system while facilitating the required common‐mode transfer for the two‐stage sampling circuits. Considering the performance of the TI ADC system in this design and the characteristics of the adopted technology, the sub‐ADC utilizes an interpolating two‐step flash ADC structure to balance speed and power consumption. Fabricated in 40‐nm CMOS technology, operating at 32 GS/s with a supply voltage of 1.1 V, the ADC achieves an SFDR of 47.93 dB and an ENOB of 6.26 bits at Nyquist, with a total power consumption of 276.4 mW.