An Incremental/Decremental Memristor Emulator Realized Using a Voltage-Controlled Second-Generation Current Conveyor (VC-CCII) and Its Application as an Artificial Synaptic Device

A grounded, charge-controlled memristor emulator (MRE) with incremental/decremental behavior is presented in this work. The proposed design utilizes a single second-generation Voltage-Controlled Current Conveyor (VCCCII) as the active element, combined with a grounded capacitor, thereby ensuring a compact and efficient implementation. Incremental and decremental memristive characteristics are realized through the incorporation of a simple switching mechanism. Simulation results, obtained in LTspice using TSMC 180-nm CMOS technology, confirm that the MRE produces pinched hysteresis loops over a wide frequency range extending up to 150MHz. The non-volatility of the emulator is further validated through memory retention tests, demonstrating its capability to preserve the stored state in the absence of external excitation. Robustness of the proposed circuit is examined through process corner analysis and thermal variation tests, ensuring reliable operation under process and environmental fluctuations. The MRE achieves an average power dissipation of only 2.12µW, highlighting its low-power characteristics. To demonstrate the potential applications of the proposed memristor its artificial synaptic plasticity is validated through example simulation. Moreover, comparative evaluations with existing memristor emulator architectures reveal the superior performance of the proposed design in terms of functionality, efficiency, and robustness.

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Publication Details

Journal
International Journal of Electrical Engineering and Computer Science
Published
2025-10-02
DOI
https://doi.org/10.37394/232027.2025.7.16
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.00

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article

An Incremental/Decremental Memristor Emulator Realized Using a Voltage-Controlled Second-Generation Current Conveyor (VC-CCII) and Its Application as an Artificial Synaptic Device

Predrag B. Petrović
International Journal of Electrical Engineering and Computer Science
Advanced Memory and Neural Computing
article

An Incremental/Decremental Memristor Emulator Realized Using a Voltage-Controlled Second-Generation Current Conveyor (VC-CCII) and Its Application as an Artificial Synaptic Device

Predrag B. Petrović
article en

Abstract

A grounded, charge-controlled memristor emulator (MRE) with incremental/decremental behavior is presented in this work. The proposed design utilizes a single second-generation Voltage-Controlled Current Conveyor (VCCCII) as the active element, combined with a grounded capacitor, thereby ensuring a compact and efficient implementation. Incremental and decremental memristive characteristics are realized through the incorporation of a simple switching mechanism. Simulation results, obtained in LTspice using TSMC 180-nm CMOS technology, confirm that the MRE produces pinched hysteresis loops over a wide frequency range extending up to 150MHz. The non-volatility of the emulator is further validated through memory retention tests, demonstrating its capability to preserve the stored state in the absence of external excitation. Robustness of the proposed circuit is examined through process corner analysis and thermal variation tests, ensuring reliable operation under process and environmental fluctuations. The MRE achieves an average power dissipation of only 2.12µW, highlighting its low-power characteristics. To demonstrate the potential applications of the proposed memristor its artificial synaptic plasticity is validated through example simulation. Moreover, comparative evaluations with existing memristor emulator architectures reveal the superior performance of the proposed design in terms of functionality, efficiency, and robustness.

International Journal of Electrical Engineering and Computer ScienceVol. 7
University of Kragujevac (RS)
Ministarstvo Prosvete, Nauke i Tehnološkog Razvoja
Openalex Percentile: Top 73%
Advanced Memory and Neural Computing
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